1. Field of the Invention
The present invention relates to a dynamic RAM which requires regular refresh operation of memory cells. Particularly, the present invention relates to a technology to automatically perform the refresh operation in its interior without the need for a refresh request from the exterior.
2. Description of the Related Art
A DRAM is suitable to attain high integration because its memory cells can be structured small. However, the DRAM requires the refresh operation in order to hold data stored in the memory cells. It is necessary to perform the refresh operation regularly on each of the memory cells. When the refresh request is generated, the refresh operation should be performed while taking priority over read operation and write operation.
In a system on which the DRAM is mounted, for example, a memory controller which controls the DRAM supplies a refresh command to the DRAM while taking priority over a read command (or a write command), when the refresh request is generated from its own refresh timer.
Meanwhile, an SRAM does not require the refresh operation, contrary to the DRAM. However, since a number of elements constituting the one-bit cell is larger than that of the DRAM, it is disadvantageous to attain large capacity.
In other words, the refresh operation has to be performed when necessary as long as a DRAM (dynamic random access memory) memory core is used. An operation area being in refresh operation cannot be accessed. As a result of this, when the refresh operation and an access request come at the same time, the access should be suspended until the completion of the refresh operation.
If the DRAM is operated as the SRAM (static random access memory) to which the refresh request is not inputted from the exterior, the refresh request needs to be regularly generated in its interior. When an access request is supplied from the exterior at this point, since the requested access is performed after the refresh operation, performing an actually single access appears to take a time equivalent to performing two operations of the memory core.
In a conventional DRAM, there is a disadvantage that its control increases in complexity because the memory controller controls the refresh operation as well. Further, since it is impossible to perform the read operation and the write operation during the refresh operation, there is a disadvantage that a data transfer rate decreases as compared with the SRAM.
Meanwhile, in the SRAM, it is difficult to attain the large capacity as described above, and further, there is a disadvantage that its chip cost is highly expensive as compared with the DRAM because its memory cells are large.
It is an object of the present invention to provide a semiconductor memory having both large capacity of a DRAM and usability of an SRAM.
It is another object of the present invention to provide the semiconductor memory which promptly responds to a request for read operation from the exterior of the memory, and whose data transfer rate is high.
It is still another object of the present invention to perform an external access in an access time taken for a single operation of a memory core, even when a refresh operation and an external access request conflict with each other.
According to one of the aspects of the semiconductor memory of the present invention, the semiconductor memory comprises a plurality of first memory blocks for storing data and a second memory block for storing data to reproduce the data stored in the first memory blocks. For example, the second memory block stores a parity bit of the first memory blocks as data. A first command generator receives a command from the exterior of the memory and generates a read command or a write command for accessing the first memory blocks, according to the received command. A second command generator generates a second command for accessing the first memory blocks or the second memory block.
When the read command and the second command access the same first memory block, that is, when the read command and the second command conflict with each other, a read control circuit accesses the first memory block according to the second command. Further, in order to operate in accordance with the read command, the read control circuit reproduces read data, which should be originally read from the first memory blocks, by using the data stored in the second memory block and the other first memory blocks. Hence, read operation time is not extended even when the read command and the second command conflict with each other. Namely, generation of the second command does not affect the read operation.
When the write command and the second command access the same first memory, a write control circuit performs operations according to commands in order in which the commands have been received. For example, when generation of the second command comes earlier than supply of the write command, the write control circuit first accesses the first memory block according to the second command, and thereafter performs write operation. At this time, the write operation in the semiconductor memory delays than usual, but changing supply timings of an address, write data, and the like from the exterior is not necessary. Hence, the generation of the second command does not affect the write operation.
As described above, users of the semiconductor memory can perform the read operation and the write operation without recognizing the conflict between the second command generated inside the semiconductor memory and the read and write commands supplied by the users. This makes it possible to provide a user-friendly semiconductor memory.
According to another aspect of the semiconductor memory of the present invention, the first and second memory blocks are structured of volatile memory cells from which data disappears over time. The second command is a refresh command generated periodically for performing refresh operation of the memory cells. Therefore, the users can use the semiconductor memory without any recognition of the refresh. For example, applying the present invention to the DRAM makes a refresh controller unnecessary in a system on which the DRAM is mounted. In other words, the users can use the DRAM in much the same way as the SRAM.
According to another aspect of the semiconductor memory of the present invention, an external write cycle, as a minimum interval between supplies of the write command, is set to be longer than an internal write cycle as actual write operation time to the first and second memory blocks. A refresh cycle can be inserted without fail while the write command is supplied a plurality of times. Hence, it is possible to prevent the data held in the memory cells from being destroyed, even while the write command is supplied many times. As a way of example, in a semiconductor memory of a clock synchronous type, when the external write cycle is set to n clock cycles (n is an integer equal to or greater than 1), the internal write cycle is set to nxe2x88x920.5 clock cycles. In this case, when the refresh cycle is 3.5 clock cycles, one refresh cycle can be inserted during seven write operations.
According to another aspect of the semiconductor memory of the present invention, when the internal write cycle is set to nxe2x88x920.5 clock cycles, every time the write command or the refresh command is supplied, a cycle switching circuit alternately operates first and second cycle generators to operate in synchronization with a first edge and a second edge of an external clock, respectively. The first cycle generator generates a first timing signal for performing an internal operation cycle in synchronization with the first edge of the external clock. The second cycle generator generates a second timing signal for performing the internal operation cycle in synchronization with the second edge of the external clock. The two cycle generators are used alternately to perform the write operation or the refresh operation, by which facilitates the control of performing each operation.
According to another aspect of the semiconductor memory of the present invention, the write control circuit includes a state control circuit. The state control circuit sequentially holds next write commands supplied during write operation to perform a write operation corresponding to one of the supplied commands which is being held after completion of the write operation. Hence, even when the refresh operation is inserted during successive write operations, it is possible to reliably perform the write operation after the refresh operation.
As described above, setting the external write cycle to be longer than the internal write cycle can reduce a delay occurring from supply of the write command to start of the write operation, every time the write operation is performed. A difference between the external write cycle and the internal write cycle may be set such that the delay is resolved by the time when the next refresh command is supplied.
According to another aspect of the semiconductor memory of the present invention, when the read command is supplied to the first memory block in write operation or refresh operation, the read control circuit reproduces read data by using the data stored in the first memory blocks except for the first memory block in the operation, and the second memory block. This makes it possible to perform the read operation without a delay in the access time even when the read operation or the write operation, and the refresh operation conflict with each other inside the semiconductor memory.
According to another aspect of the semiconductor memory of the present invention, only one of the first and second memory blocks is refreshed in response to the refresh command. This enables secure reproduction of read data by using the other memory blocks even when the first memory block on which a read operation is to be performed is in refresh operation. In case where the second memory block is in refresh operation, data can be read directly from the first memory block corresponding to the read command.
According to another aspect of the semiconductor memory of the present invention, a refresh counter sequentially indicates on which of the first and second memory blocks a refresh operation is to be performed. Upon the supply of the read command to the memory block indicated by the refresh counter, the read control circuit reproduces read data by using the data stored in the second memory block, even though the refresh operation is not performed on the indicated memory block. Hence, even when a refresh request is generated immediately before or after the read command, the read control circuit can reproduce read data by using the other memory blocks. Determining in advance which of normal operation and reproduction operation is performed according to a value of the refresh counter makes it possible to facilitate the control of the read control circuit, and further to realize a simple circuit configuration.
According to another aspect of the semiconductor memory of the present invention, the semiconductor memory includes a plurality of data input/output terminals for inputting/outputting data. The first memory blocks are respectively formed corresponding to the data input/output terminals which are different from each other. Namely, in the read operation, all of the first memory blocks continuously operate to output the read data. When a refresh request is generated, unreadable data among read data outputted from the data input/output terminals due to the refresh operation is always only one bit. This allows secure reproduction of data stored in the first memory block being in refresh by using the other first memory blocks and the second memory block.
Meanwhile, in a case where the first memory blocks are formed corresponding to addresses, a single first memory block corresponds to a plurality of data input/output terminals. This requires an increase in capacity of the second memory block for reproducing read data. Further, the read control of the read control circuit becomes more complex.
According to another aspect of the semiconductor memory of the present invention, the semiconductor memory includes a plurality of memory groups composed of the first memory blocks and the second memory block. The refresh operation in response to the refresh command is performed on any of the first memory blocks or the second memory block in the plurality of memory groups. Namely, the read operation and the write operation are performed for every memory group, and the refresh operation is performed for the plurality of memory groups. This results in minimizing a necessary generation number of the refresh commands for refreshing all of the memory cells and in lengthening an generation interval of the refresh commands.
According to another aspect of the semiconductor memory of the present invention, the first and second memory blocks are arranged in a first direction in each of the memory groups. The memory groups are arranged in a second direction orthogonal to the first direction. The refresh operation in response to the refresh command is performed on the first or second memory blocks aligned in the second direction. Arranging the memory blocks simultaneously activated in read and write operations in the first direction and the memory blocks simultaneously activated in refresh operation in the second direction, for example, allows the plurality of memory groups to share sense amplifiers, decoders or, the like, and also allows reduction in chip size.
According to another aspect of the semiconductor memory of the present invention, column selecting switches, column decoders, word decoders, and sense amplifiers are arranged in the first direction, whereby these circuits can be shared by the plurality of memory groups, and the chip size can be reduced.
According to another aspect of the semiconductor memory of the present invention, a clock generator receives an external clock, and generates an internal clock as a synchronizing signal of an internal circuit. A first command receiver circuit receives the write command in synchronization with a first edge of the external clock. A second command receiver circuit receives the refresh command in synchronization with a second edge of the external clock. An arbiter determines an order in which the write command and the refresh command received in the first and second command receiver circuits are to be performed. Shifting receipts of the write command and the refresh command by at least half a clock or more makes it easier to determine the order of command receipt. Namely, the arbiter can be structured simply.
According to another aspect of the semiconductor memory of the present invention, a clock generator receives an external clock, and generates an internal clock as a synchronizing signal of an internal circuit. The first command generator receives commands in synchronization with a first edge and a second edge of the external clock, respectively, and generates the read command or the write command according to the received commands. For example, the first edge is an up edge and the second edge is a down edge subsequent to the up edge. Since the commands are respectively received in synchronization with the two adjacent edges, it is possible to shorten an interval between inputs of the commands and to shorten the access time.
According to another aspect of the semiconductor memory of the present invention, a clock generator receives an external clock, and generates an internal clock as a synchronizing signal of an internal circuit. A data input circuit successively inputs write data in synchronization with the external clock, in response to a single write command. A length of time for the first command generator to start receiving data from reception of the write command changes according to a burst length which is a number of times the write data is received corresponding to the single write command. Hence, it is possible to increase efficiency in use of data buses.
According to another aspect of the semiconductor memory of the present invention, the semiconductor includes a plurality of banks operating independently. Each of the banks includes the plurality of first memory blocks and the second memory block. A clock generator receives an external clock, and generates an internal clock as a synchronizing signal of an internal circuit. A data output circuit successively outputs read data in synchronization with the external clock, in response to a single read command. A data input circuit successively inputs write data in synchronization with the external clock, in response to a single write command. In sequentially accessing the banks which are different from each other, minimum intervals between supplies of the read command and the write command change according to a burst length as a number of times the read data is outputted corresponding to the single read command, and a number of times the write data is received corresponding to the single write command. Setting specifications for supplying the commands according to internal operation of the semiconductor memory enables a simple configuration of the control circuit for controlling the internal operation.
According to another aspect of the semiconductor memory of the present invention, the semiconductor memory includes 2m read data bus lines respectively formed corresponding to data input/output terminals. A data switching circuit determines to which of the read data bus lines read data from the memory block is transmitted. A parallel/serial conversion circuit converts parallel read data transmitted through the read data bus line into serial data. The burst length can be set to m or 2m (m is an integer equal to or greater than 1). The data switching circuit transmits the read data to the parallel/serial conversion circuit by using all of the 2m read data bus lines, when the burst length is set to 2m. Further, the data switching circuit transmits m pieces of the read data to the parallel/serial conversion circuit by using the m data bus lines alternately, when the burst length is set to m. Hence, it is possible to ease data transmission cycles of the data buses, especially when the burst length is m. As a result of this, the operation with a high clock frequency can be realized.
According to another aspect of the semiconductor memory of the present invention, the semiconductor memory includes 2m write data bus lines respectively formed corresponding to data input/output terminals. A data switching circuit determines to which of the write data bus lines write data supplied from the exterior is transmitted. A serial/parallel conversion circuit converts serial write data supplied from the exterior into parallel data to be outputted to the write data bus lines. The serial/parallel conversion circuit outputs 2m pieces of the converted parallel write data simultaneously to the 2m write data bus lines, when the burst length is set to 2m. The serial/parallel conversion circuit outputs m pieces of the converted parallel write data alternately to the m write data bus lines, when the burst length is set to m. Hence, it is possible to ease data transmission cycles of the data buses, especially when the burst length is m. As a result of this, the operation with a high clock frequency can be realized.
According to another aspect of the semiconductor memory of the present invention, a clock generator receives an external clock, and generates an internal clock as a synchronizing signal of an internal circuit. A data input circuit successively inputs write data in synchronization with the external clock, in response to a single write command. A data masking control circuit masks write operation on the memory blocks, for each Write data inputted in synchronization with the external clock. All of the write data supplied at the same timing is written or masked so that the data stored in the second memory block can be easily generated. Hence, the circuit for generating the data stored in the second memory block can be simplified.
According to another aspect of the semiconductor memory of the present invention. A data output circuit outputs read data from the memory blocks in synchronization with an internal data strobe signal generated from the internal clock. A data input circuit receives write data supplied from the exterior in synchronization with an external data strobe signal supplied from the exterior. A mode register determines whether the external and internal data strobe signals are inputted/outputted through the same terminal or respectively through different terminals. Hence, it is possible to respond to various needs of the users.
According to another aspect of the semiconductor memory of the present invention, a refresh counter indicates a memory cell on which a refresh operation is to be performed, and counts up with every refresh request. Lower bit(s) of the refresh counter correspond(s) to a bank address for selecting the bank. The refresh operation is performed for each bank. Reducing the number of the refresh control circuits to concurrently operate can further decrease a peak current during the refresh operation. Further, since the plurality of banks are refreshed alternately, generation intervals of the refresh requests can be shortened as compared with the case where the same bank is successively refreshed. Therefore, even with a low operating frequency, it is possible to satisfy a necessary period for refreshing all of the memory cells. In other words, the lower limit of an operating frequency can be set to a lower value.
According to another aspect of the semiconductor memory of the present invention, the semiconductor memory comprises a memory core including a plurality of memory blocks for distributing and storing a plurality of bit data corresponding to the same address, and a control circuit for controlling the memory core. The control circuit is able to control refresh operations of the plurality of memory blocks independently so as to perform refresh operations on one memory block and another memory block at different timings.
Independently performing the refresh operation on the plurality of memory blocks makes it possible to concurrently process an access request from the exterior and the refresh operation. That is, the refresh operation on a part of the memory blocks and an access to the other memory blocks from the exterior can be performed at the same timing. Thereby, the read operation can be realized within an access time taken for a single operation of the memory core. Namely, the read operation can be performed quickly.